Block-Level Design Optimization for Sub-100-nm Cell Height Libraries with Stacked Transistor

We benchmark block-level power, performance and area scaling for a scaled architecture with 80 nm cell height based on stacked, stepped nanosheet transistors with backside power delivery. In addition to a base 5-track (5T) library, we evaluate several variant libraries, including high-density 4T, high-performance, double height, low-power and cross-couple (XC)-enabled. We demonstrate library optimization with these design variants enable attractive power, performance and area scaling for the Angstrom era of transistor scaling.