Design and Experimental Technology for 0.1-μm Gate-Length Low-Temperature Operation FET's
- George A. Sai-Halasz
- Matthew R. Wordeman
- et al.
- 1987
- IEEE Electron Device Letters
Publications
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66 results for Phillip Restle
BEOL compatible high-capacitance MIMCAP structure using a novel high k material
- P. Jamison
- John Massey
- et al.
- 2020
- IMCS 2020
Thermal analysis of multi-layer functional 3D logic stacks
- Michael Scheuermann
- Shurong Tian
- et al.
- 2016
- 3DIC 2016
Resonant clock mega-mesh for the IBM z13™
- David Shan
- Phillip Restle
- et al.
- 2015
- VLSI Circuits 2015
Optimization and modeling of resonant clocking inductors for the POWER8TM microprocessor
- Robert Groves
- Phillip Restle
- et al.
- 2014
- CICC 2014
PACMAN: Driving nonuniform clock grid loads for low-skew robust clock network
- Nancy Y. Zhou
- Phillip Restle
- et al.
- 2014
- SLIP 2014
The POWER8™ processor: Designed for big data, analytics, and cloud environments
- Joshua Friedrich
- Hung Le
- et al.
- 2014
- ICICDT 2014
On-chip circuit for measuring multi-GHz clock signal waveforms
- Keith A. Jenkins
- P. Restle
- et al.
- 2013
- VTS 2013
A shorted global clock design for multi-GHz 3D stacked chips
- Liang-Teck Pang
- Phillip J. Restle
- et al.
- 2012
- VLSI Circuits 2012
Myth busters: Microprocessor clocking is from Mars, ASICs clocking is from Venus
- Joseph Kozhaya
- Phillip Restle
- et al.
- 2011
- ICCAD 2011