Design of resonant global clock distributions
Steven C. Chan, Kenneth L. Shepard, et al.
ICCD 2003
Resonant clock distributions have the potential to save power by recycling energy from cycle-to-cycle while at the same time improving performance by reducing the clock distribution latency and filtering out non-periodic noise. While these features have been successfully demonstrated in several small-scale experiments, there remained a number of concerns about whether these techniques would scale to a product application. By modifying the Cell Broadband Engine Processor to incorporate a large resonant global clock network, power savings with full functionality is demonstrated over a 20% range in clock frequencies, and a 68 Watt power savings at 4 GHz. This was achieved by changing one wiring level and adding an additional thick copper level to create inductors and capacitors. © 2006 IEEE.
Steven C. Chan, Kenneth L. Shepard, et al.
ICCD 2003
Brian Vanderpool, Phillip J. Restle, et al.
IEEE JSSC
Phillip J. Restle, Albert Ruehli, et al.
ADMETA 2000
Steven C. Chan, Kenneth L. Shepard, et al.
IEEE Journal of Solid-State Circuits