Technology-circuit co-design of asymmetric SRAM cells for read stability improvement
- Jae-Joon Kim
- Rahul Rao
- et al.
- 2010
- CICC 2010
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38 results for R.M. Rao
A centralized supply voltage and local body bias-based compensation approach to mitigate within-die process variation
- Amlan Ghosh
- Rahul M. Rao
- et al.
- 2009
- ISLPED 2009
Impact of NBTI and PBTI in SRAM bit-cells: Relative sensitivities and guidelines for application-specific target stability/performance
- Aditya Bansal
- Rahul Rao
- et al.
- 2009
- IRPS 2009
A precise negative bias temperature instability sensor using slew-rate monitor circuitry
- Amlan Ghosh
- Richard B. Brown
- et al.
- 2009
- ISCAS 2009
Variability and power management in sub-100nm SOI technology for reliable high performance systems
- Koushik Das
- Kerry Bernstein
- et al.
- 2008
- IEEE International SOI Conference 2008
Ring oscillator circuit structures for measurement of isolated NBTI/PBTI effects
- Jae-Joon Kim
- Rahul Rao
- et al.
- 2008
- ICICDT 2008
Capacitive coupling based transient negative bit-line voltage (tran-NBL) scheme for improving write-ability of SRAM design in nanometer technologies
- S. Mukhopadhyay
- R.M. Rao
- et al.
- 2008
- ISCAS 2008
On-chip process variation detection and compensation using delay and slew-rate monitoring circuits
- Amlan Ghosh
- Rahul M. Rao
- et al.
- 2008
- ISQED 2008
On-chip process variation detection using slew-rate monitoring circuit
- Amlan Ghosh
- Rahul M. Rao
- et al.
- 2008
- VLSID 2008
Evaluation and optimization of FinFET quantization error in porting a design from planar silicon technology
- R.M. Rao
- J. Kim
- et al.
- 2007
- SOI 2007