Experimental analysis and modeling of self heating effect in dielectric isolated planar and fin devices
- S. Lee
- Richard A. Wachnik
- et al.
- 2013
- VLSI Technology 2013
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36 results for Shreesh Narasimha
Advanced modeling and optimization of high performance 32nm HKMG SOI CMOS for RF/analog SoC applications
- Sungjae Lee
- J. Johnson
- et al.
- 2012
- VLSI Technology 2012
On the systematic analysis of ring-delay performance using statistical behavior model
- Q. Liang
- B. Greene
- et al.
- 2009
- ISDRS 2009
Hole transport in nanoscale p-type MOSFET SOI devices with high strain
- H. Nayfeh
- S.-J. Jeng
- et al.
- 2007
- DRC 2007
CMOS fabricated by hybrid-orientation technology (HOT)
- Bin Yang
- M. Yang
- et al.
- 2007
- IEDST 2007
Simulation study on channel length scaling of high performance partially depleted metal gate and poly gate SOI MOSFETs
- Wang Xinlin
- Andres Bryant
- et al.
- 2006
- SISPAD 2006
Body voltage and history effect sensitivity to key device parameters in 90nm PD-SOI
- S. Kawanaka
- M.B. Ketchen
- et al.
- 2004
- IEEE International SOI Conference 2004
A 243-GHz Ft and 208-GHz Fmax, 90-nm SOI CMOS SoC technology with low-power millimeter-wave digital and RF circuit capability
- Noah Zamdmer
- Jonghae Kim
- et al.
- 2004
- VLSI Technology 2004
Suitability of scaled SOI CMOS for high-frequency analog circuits
- N. Zamdmer
- J.O. Plouchart
- et al.
- 2002
- ESSDERC 2002
Breakdown data generation and in-die deconvolution methodology to address BEOL and MOL dielectric breakdown challenges
- F. Chen
- Carole Graas
- et al.
- 2015
- Microelectronics Reliability