CMOS fabricated by hybrid-orientation technology (HOT)
- Bin Yang
- M. Yang
- et al.
- 2007
- IEDST 2007
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36 results for Shreesh Narasimha
Optimization of silicon technology for the IBM System z9
- Daniel J. Poindexter
- Scott R. Stiffler
- et al.
- 2007
- IBM J. Res. Dev
High performance 45-nm SOI technology with enhanced strain, porous low-k BEOL, and immersion lithography
- S. Narasimha
- K. Onishi
- et al.
- 2006
- IEDM 2006
Challenges and opportunities for high performance 32 nm CMOS technology
- J. Sleight
- I. Lauer
- et al.
- 2006
- IEDM 2006
Simulation study on channel length scaling of high performance partially depleted metal gate and poly gate SOI MOSFETs
- Wang Xinlin
- Andres Bryant
- et al.
- 2006
- SISPAD 2006
Gate-dielectric permitivity and metal-gate work-function tradeoff in Lmet = 25 nm PDSOI device characteristics
- Dechao Guo
- Andres Bryant
- et al.
- 2006
- IEEE Electron Device Letters
An integrated methodology for accurate extraction of S/D series resistance components in nanoscale MOSFETs
- Seong-Dong Kim
- Shreesh Narasimha
- et al.
- 2005
- IEDM 2005
A 243-GHz Ft and 208-GHz Fmax, 90-nm SOI CMOS SoC technology with low-power mmWave digital and RF circuit capability
- Jean-Olivier Plouchart
- Noah Zamdmer
- et al.
- 2005
- IEEE Transactions on Electron Devices
Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing
- H.S. Yang
- R. Malik
- et al.
- 2004
- IEDM 2004
Body voltage and history effect sensitivity to key device parameters in 90nm PD-SOI
- S. Kawanaka
- M.B. Ketchen
- et al.
- 2004
- IEEE International SOI Conference 2004