Electrical characterization of FinFETs with fins formed by directed self assembly at 29 nm fin pitch using a self-aligned fin customization scheme
- Hsinyu Tsai
- Hiroyuki Miyazoe
- et al.
- 2014
- IEDM 2014
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27 results for Josephine B. Chang
Density scaling with gate-all-around silicon nanowire MOSFETs for the 10 nm node and beyond
- Sarunya Bangsaruntip
- K. Balakrishnan
- et al.
- 2013
- IEDM 2013
Wafer scale fabrication of carbon nanotube FETs with embedded poly-gates
- Shu-Jen Han
- Josephine Chang
- et al.
- 2010
- IEDM 2010
Fully depleted extremely thin SOI for mainstream 20nm low-power technology and beyond
- Ali Khakifirooz
- Kangguo Cheng
- et al.
- 2010
- ISSCC 2010
Challenges and solutions of FinFET integration in an SRAM cell and a logic circuit for 22 nm node and beyond
- H. Kawasaki
- V.S. Basker
- et al.
- 2009
- IEDM 2009
Trigate 6T SRAM scaling to 0.06 μm2
- M. Guillorn
- J. Chang
- et al.
- 2009
- IEDM 2009
Demonstration of highly scaled FinFET SRAM cells with high-Κ/metal gate and investigation of characteristic variability for the 32 nm node and beyond
- H. Kawasaki
- M. Khater
- et al.
- 2008
- IEDM 2008
22 nm technology compatible fully functional 0.1 μm 2 6T-sram cell
- B. Haran
- A. Kumar
- et al.
- 2008
- IEDM 2008
Stress memorization in high-performance FDSOI devices with ultra-thin silicon channels and 25nm gate lengths
- D. Singh
- J. Sleight
- et al.
- 2005
- IEDM 2005
Dopant-segregation technique for leakage reduction and performance improvement in trigate transistors without raised source/drain epitaxy
- Fei Liu
- Zhen Zhang
- et al.
- 2014
- IEEE Electron Device Letters