A Wide Power Supply Range, Wide Tuning Range, All Static CMOS All Digital PLL in 65 nm SOI
- José A. Tierno
- Alexander V. Rylyakov
- et al.
- 2008
- IEEE Journal of Solid-State Circuits
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156 results for Alexander V. Rylyakov
An 11 Gb/s 2.4 mW half-rate sampling 2-tap DFE receiver in 65nm CMOS
- Alexander Rylyakov
- 2007
- VLSI Circuits 2007
Power-efficient decision-feedback equalizers for multi-Gb/s CMOS serial links (invited)
- John F. Bulzacchelli
- Alexander V. Rylyakov
- et al.
- 2007
- RFIC 2007
A 5-mW 6-Gb/s quarter-rate sampling receiver with a 2-Tap DFE using soft decisions
- Koon-Lun Jackie Wong
- Alexander Rylyakov
- et al.
- 2007
- IEEE Journal of Solid-State Circuits
A 6.0-mW 10.0-Gb/s receiver with switched-capacitor summation DFE
- Azita Emami-Neyestanak
- Aida Varzaghani
- et al.
- 2007
- IEEE Journal of Solid-State Circuits
A wide power-supply range (0.5V-to-1.3V) wide tuning range (500 MHz-to-8 GHz) all-static CMOS AD PLL in 65nm SOI
- A. Rylyakov
- J. Tierno
- et al.
- 2007
- ISSCC 2007
A 10-Gb/s 5-tap DFE/4-tap FFE transceiver in 90-nm CMOS technology
- John F. Bulzacchelli
- Mounir Meghelli
- et al.
- 2006
- IEEE Journal of Solid-State Circuits
A 10Gb/s 5-tap-DFE/4-tap-FFE transceiver in 90nm CMOS
- M. Meghelli
- S. Rylov
- et al.
- 2006
- ISSCC 2006
A 5-mW 6-Gb/s quarter-rate sampling receiver with a 2-tap DFE using soft decisions
- Koon-Lun Jackie Wong
- Alexander Rylyakov
- et al.
- 2006
- VLSI Circuits 2006
A low-power receiver with switched-capacitor summation DFE
- Azita Emami-Neyestanak
- Aida Varzaghani
- et al.
- 2006
- VLSI Circuits 2006