An integral path self-calibration scheme for a dual-loop PLL
- Mark Ferriss
- Jean-Olivier Plouchart
- et al.
- 2013
- IEEE JSSC
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156 results for Alexander V. Rylyakov
A 23.5 GHz PLL with an adaptively biased VCO in 32 nm SOI-CMOS
- Jean-Olivier Plouchart
- Mark A. Ferriss
- et al.
- 2013
- IEEE TCAS-I
A 90nm CMOS integrated Nano-Photonics technology for 25Gbps WDM optical communications applications
- Solomon Assefa
- Steven Shank
- et al.
- 2012
- IEDM 2012
Monolithic integration of silicon nanophotonics with CMOS
- Solomon Assefa
- William M. J. Green
- et al.
- 2012
- IPC 2012
Ultra low power 10-to 25-Gb/s CMOS-driven VCSEL links
- Jonathan E. Proesel
- Clint L. Schow
- et al.
- 2012
- OFC 2012
A 25-Gb/s 49-mW CMOS-driven equalized optical link
- Benjamin G. Lee
- Jonathan E. Proesel
- et al.
- 2012
- IPC 2012
Monolithic integration of CMOS and silicon nanophotonics for optical interconnects
- Solomon Assefa
- William M. J. Green
- et al.
- 2012
- FiO 2012
Electrical interconnect design for testing of high-speed IC transceivers
- Renato Rimolo-Donadio
- Christian Baks
- et al.
- 2012
- EPEPS 2012
A 55Gb/s directly modulated 850nm VCSEL-based optical link
- Daniel M. Kuchta
- Alexander V. Rylyakov
- et al.
- 2012
- IPC 2012
A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS
- Jean-Olivier Plouchart
- Mark A. Ferriss
- et al.
- 2012
- CICC 2012