Publications

This is our catalog of publications authored by IBM researchers, in collaboration with the global research community. It’s an ever-growing body of work that shows why IBM is one of the most important contributors to modern computing.

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51 results for Jeffrey W. Sleight

High-performance Si_1-xGe_x channel on insulator trigate PFETs featuring an implant-free process and aggressively-scaled fin and gate dimensions
- - P. Hashemi
  - M. Kobayashi
  - et al.
- 2013
- VLSI Technology 2013
Gate-all-around silicon nanowire 25-stage CMOS ring oscillators with diameter down to 3 nm
- - Sarunya Bangsaruntip
  - A. Majumdar
  - et al.
- 2010
- VLSI Technology 2010
Gate-all-around silicon nanowire MOSFETs and circuits
- - Jeffrey W. Sleight
  - Sarunya Bangsaruntip
  - et al.
- 2010
- DRC 2010
Interface state density measurements in gated p-i-n silicon nanowires as a function of the nanowire diameter
- - Guy Cohen
  - E. Cartier
  - et al.
- 2010
- DRC 2010
High performance and highly uniform metal hi-k gate-all-around silicon nanowire mosfets
- - Jeffrey W. Sleight
  - Sarunya Bangsaruntip
  - et al.
- 2010
- ECS Transactions
Are Si/SiGe tunneling field-effect transistors a good idea?
- - Steven J. Koester
  - Isaac Lauer
  - et al.
- 2010
- ECS Transactions
High performance 32nm SOI CMOS with high-k/metal gate and 0.149μm ² SRAM and ultra low-k back end with eleven levels of copper
- - B. Greene
  - Q. Liang
  - et al.
- 2009
- VLSI Technology 2009
Upside-down FETS
- - D.C. La Tulipe Jr.
  - D.J. Frank
  - et al.
- 2008
- IEEE International SOI Conference 2008
Measurement of silicon nanowires carrier mobility and its size dependence
- - O. Gunawan
  - L. Sekaric
  - et al.
- 2008
- DRC 2008
High-performance high-κ/metal gates for 45nm CMOS and beyond with gate-first processing
- - M. Chudzik
  - B. Doris
  - et al.
- 2007
- VLSI Technology 2007