Stable SRAM cell design for the 32 nm node and beyond
- Leland Chang
- David M. Fried
- et al.
- 2005
- VLSI Technology 2005
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51 results for Jeffrey W. Sleight
Aggressively scaled (0.143 μm 2) 6T-SRAM cell for the 32 nm node and beyond
- D. Fried
- J. Hergenrother
- et al.
- 2004
- IEDM 2004
Highly Manufacturable 40-50 GHz VCOs in a 120nm System-on-Chip SOI Technology
- Jonghae Kim
- Jean-Olivier Plouchart
- et al.
- 2003
- IEDM 2003
Controlling floating-body effects for 0.13μm and 0.10μm SOI CMOS
- S.K.H. Fung
- N. Zamdmer
- et al.
- 2000
- IEDM 2000
Partially depleted silicon-on-insulator (SOI): A device design/modeling and circuit perspective
- F. Assaderaghi
- G. Shahidi
- et al.
- 2000
- ICM 2000
Design of a high performance PD SOI for the 0.18 μm technology generation
- M. Sherony
- S.-H. Lo
- et al.
- 2000
- ICM 2000
Partially-depleted SOI compact model - formulation and parameter extraction
- S.K.H. Fung
- L. Wagner
- et al.
- 2000
- VLSI Technology 2000
High performance 0.18 μm SOI CMOS technology
- E. Leobandung
- E. Barth
- et al.
- 1999
- IEDM 1999
0.22 μm CMOS-SOI technology with a Cu BEOL
- A. Ajmera
- J. Sleight
- et al.
- 1999
- VLSI Technology 1999
Sub-60 nm physical gate length SOI CMOS
- I.Y. Yang
- K. Chen
- et al.
- 1999
- IEDM 1999