Chip-level power-performance optimization through thermally-driven across-chip variation (ACV) reduction
- X. Yu
- Oleg Gluschenkov
- et al.
- 2011
- IEDM 2011
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14 results for Ronald Logan
High-performance sub-0.08 μm CMOS with dual gate oxide and 9.7 ps inverter delay
- M. Hargrove
- S.W. Crowder
- et al.
- 1998
- IEDM 1998
On “Effective Channel Length” in 0.1-µm MOSFET's
- Yuan Taur
- Yuh-Jier Mii
- et al.
- 1995
- IEEE Electron Device Letters
A simple hardware-based statistical model on 65nm SOI CMOS technology
- Q. Liang
- J.B. Johnson
- et al.
- 2007
- ISDRS 2007
RTA-driven intra-die variations in stage delay, and parametric sensitivities for 65nm technology
- I. Ahsan
- N. Zamdmer
- et al.
- 2006
- VLSI Technology 2006
High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell
- E. Leobandung
- H. Nayakama
- et al.
- 2005
- VLSI Technology 2005
0.18 μm high-performance logic technology
- S.W. Crowder
- S. Greco
- et al.
- 1999
- VLSI Technology 1999
Asymmetry in effective-channel length of n- and p-MOSFETs
- L.R. Logan
- Y. Taur
- et al.
- 1997
- SISPAD 1997
A room temperature 0.1 μm CMOS on SOI
- G. Shahidi
- C. Blair
- et al.
- 1993
- VLSI Technology 1993
Continuous prediction of manufacturing performance throughout the production lifecycle
- Sholom M. Weiss
- Amit Dhurandhar
- et al.
- 2014
- Journal of Intelligent Manufacturing