Optimal dual-VT design in sub-100-nm PD/SOI and double-gate technologies
- Aditya Bansal
- Jae-Joon Kim
- et al.
- 2008
- IEEE Transactions on Electron Devices
Publications
Date
Featured collections
Popular topics
79 results for Keunwoo Kim
Device design and optimization methodology for leakage and variability reduction in sub-45-nm FD/SOI SRAM
- Saibal Mukhopadhyay
- Keunwoo Kim
- et al.
- 2008
- IEEE Transactions on Electron Devices
Low-power high-performance asymmetrical double-gate circuits using back-gate-controlled wide-tunable-range diode voltage
- Keunwoo Kim
- Ching-Te Chuang
- et al.
- 2007
- IEEE Transactions on Electron Devices
Random dopant fluctuation in limited-width FinFET technologies
- Meng-Hsueh Chiang
- Jeng-Nan Lin
- et al.
- 2007
- IEEE Transactions on Electron Devices
Estimation of gate-to-channel tunneling current in ultra-thin oxide sub-50 nm double gate devices
- Saibal Mukhopadhyay
- Keunwoo Kim
- et al.
- 2007
- Microelectronics Journal
The impact of device footprint scaling on high-performance CMOS logic technology
- Jie Deng
- Keunwoo Kim
- et al.
- 2007
- IEEE Transactions on Electron Devices
High-density data-retention power gating structure using a four-terminal double-gate device
- K. Kim
- K. Das
- et al.
- 2007
- International Journal of Electronics
Modeling and analysis of leakage currents in double-gate technologies
- Saibal Mukhopadhyay
- Keunwoo Kim
- et al.
- 2006
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
High-density reduced-stack logic circuit techniques using independent-gate controlled double-gate devices
- Meng-Hsueh Chiang
- Keunwoo Kim
- et al.
- 2006
- IEEE Transactions on Electron Devices
Novel high-density low-power logic circuit techniques using DG devices
- Meng-Hsueh Chiang
- Keunwoo Kim
- et al.
- 2005
- IEEE Transactions on Electron Devices