Ultralow-voltage minimum-energy CMOS
- Scott Hanson
- Bo Zhai
- et al.
- 2006
- IBM J. Res. Dev
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29 results for A. Bryant
Simulation study on channel length scaling of high performance partially depleted metal gate and poly gate SOI MOSFETs
- Wang Xinlin
- Andres Bryant
- et al.
- 2006
- SISPAD 2006
Gate-dielectric permitivity and metal-gate work-function tradeoff in Lmet = 25 nm PDSOI device characteristics
- Dechao Guo
- Andres Bryant
- et al.
- 2006
- IEEE Electron Device Letters
Investigation of CMOS devices with embedded SiGe source/drain on hybrid orientation substrates
- Qiqing Ouyang
- Min Yang
- et al.
- 2005
- VLSI Technology 2005
Simulation analysis of series resistance for SOI MOSFET in nanometer regime
- Xinlin Wang
- Phil Oldiges
- et al.
- 2005
- SISPAD 2005
Dual stress liner enhancement in hybrid orientation technology
- C. Sheraw
- M. Yang
- et al.
- 2005
- VLSI Technology 2005
Performance comparison and channel length scaling of strained Si FETs on SiGe-on-insulator (SGOI)
- J. Cai
- K. Rim
- et al.
- 2004
- IEDM 2004
Low-power CMOS at Vdd=4kT/q
- A. Bryant
- J. Brown
- et al.
- 2001
- DRC 2001
0.22 μm CMOS-SOI technology with a Cu BEOL
- A. Ajmera
- J. Sleight
- et al.
- 1999
- VLSI Technology 1999