0.026μm2 high performance Embedded DRAM in 22nm technology for server and SOC applications
- C. Pei
- G. Wang
- et al.
- 2014
- IEDM 2014
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11 results for G. Wang
High performance 14nm SOI FinFET CMOS technology with 0.0174μm2 embedded DRAM and 15 levels of Cu metallization
- C.-H.C-H. Lin
- Brian Greene
- et al.
- 2014
- IEDM 2014
2nd Generation dual-channel optimization with cSiGe for 22nm HP technology and beyond
- C. Ortolland
- Daniel Jaeger
- et al.
- 2013
- IEDM 2013
22nm High-performance SOI technology featuring dual-embedded stressors, Epi-Plate High-K deep-trench embedded DRAM and self-aligned Via 15LM BEOL
- S. Narasimha
- P. Chang
- et al.
- 2012
- IEDM 2012
Scaling deep trench based eDRAM on SOI to 32nm and beyond
- G. Wang
- D. Anand
- et al.
- 2009
- IEDM 2009
A 0.127 μm2 high performance 65 nm SOI based embedded DRAM for on-processor applications
- G. Wang
- K. Cheng
- et al.
- 2006
- IEDM 2006
Embedded memory considerations in SOI
- G. Wang
- Carl Radens
- et al.
- 2010
- IEEE International SOI Conference 2010
Analysis of retention time distribution of embedded DRAM - A new mMethod to characterize across-chip threshold voltage variation
- W. Kong
- P. Parries
- et al.
- 2008
- IEEE ITC 2008
Access transistor design and optimization for 65/45nm high performance SOI eDRAM
- G. Wang
- P. Parries
- et al.
- 2008
- VLSI-TSA 2008
A 0.168μm 2/0.11μm 2 highly scalable high performance embedded DRAM cell for 90/65-nm logic applications
- G. Wang
- P. Parries
- et al.
- 2005
- VLSI Technology 2005