Stress proximity technique for performance improvement with dual stress liner at 45nm technology and beyond
- X. Chen
- S. Fang
- et al.
- 2006
- VLSI Technology 2006
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26 results for X. Chen
Process induced stress for CMOS performance improvement
- S. Fang
- S.S. Tan
- et al.
- 2006
- ICSICT 2006
Dual stress liner enhancement in hybrid orientation technology
- C. Sheraw
- M. Yang
- et al.
- 2005
- VLSI Technology 2005
Integration of copper and fluorosilicate glass for 0.18 μm interconnections
- E. Barth
- T. Ivers
- et al.
- 2000
- IITC 2000
0.18 μm high-performance logic technology
- S.W. Crowder
- S. Greco
- et al.
- 1999
- VLSI Technology 1999
Reduced electromigration of Cu wires by surface coating
- C.-K. Hu
- L. Gignac
- et al.
- 2002
- Applied Physics Letters