Publications

28 results for D. Schepis

(110) Channel, SiON gate-dielectric PMOS with record high I_on=1 mA/μm through channel stress and source drain external resistance (R _ext) engineering
- - B. Yang
  - A. Waite
  - et al.
- 2007
- IEDM 2007
High performance 45-nm SOI technology with enhanced strain, porous low-k BEOL, and immersion lithography
- - S. Narasimha
  - K. Onishi
  - et al.
- 2006
- IEDM 2006
Novel enhanced stressor with graded embedded SiGe source/drain for high performance CMOS devices
- - J.-P. Han
  - H. Utomo
  - et al.
- 2006
- IEDM 2006
High performance 65 nm SOI technology with enhanced transistor strain and advanced-low-K BEOL
- - W.-H. Lee
  - A. Waite
  - et al.
- 2005
- IEDM 2005
Integration and optimization of embedded-SiGe, compressive and tensile stressed liner films, and stress memorization in advanced SOI CMOS technologies
- - M. Horstmann
  - A. Wei
  - et al.
- 2005
- IEDM 2005
Design of high performance PFETs with strained Si channel and laser anneal
- - Z. Luo
  - Y.F. Chong
  - et al.
- 2005
- IEDM 2005
Qualification of 300 mm SOI CMOS substrate material: Readiness for development and manufacturing
- - H.J. Hovel
  - M. Almonte
  - et al.
- 2004
- Solid-State Electronics
A high performance 90 nm SOI technology with 0.992 μm² 6T-SRAM cell
- - Mukesh Khare
  - S. Ku
  - et al.
- 2002
- IEDM 2002
0.22 μm CMOS-SOI technology with a Cu BEOL
- - A. Ajmera
  - J. Sleight
  - et al.
- 1999
- VLSI Technology 1999
High performance 0.18 μm SOI CMOS technology
- - E. Leobandung
  - E. Barth
  - et al.
- 1999
- IEDM 1999