A 45nm low power bulk technology featuring carbon co-implantation and laser anneal on 45°-rotated substrate
- J. Yuan
- V. Chan
- et al.
- 2008
- ICSICT 2008
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38 results for Victor Chan
High performance transistors featured in an aggressively scaled 45nm bulk CMOS technology
- Z. Luo
- N. Rovedo
- et al.
- 2007
- VLSI Technology 2007
Characterization and analysis of gate-induced-drain-leakage current in 45 nm CMOS technology
- Xiaobin Yuan
- Jae-Eun Park
- et al.
- 2007
- IIRW 2007
Uniaxial strain relaxation on ultra-thin strained-Si directly on insulator (SSDOI) substrates
- Haizhou Yin
- Z. Ren
- et al.
- 2006
- ICSICT 2006
Integration of local stress techniques with strained-Si directly on insulator (SSDOI) substrates
- Haizhou Yin
- Z. Ren
- et al.
- 2006
- VLSI Technology 2006
Process induced stress for CMOS performance improvement
- S. Fang
- S.S. Tan
- et al.
- 2006
- ICSICT 2006
Interaction of middle-of-line (MOL) temperature and mechanical stress on 90nm hi-speed device performance and reliability
- K.Y. Lim
- V. Chan
- et al.
- 2005
- ESSDERC 2005
Dual stress liner enhancement in hybrid orientation technology
- C. Sheraw
- M. Yang
- et al.
- 2005
- VLSI Technology 2005
On the scalability and carrier transport of advanced CMOS devices
- Meikei Ieong
- Leland Chang
- et al.
- 2005
- ICICDT 2005
Strain for CMOS performance improvement
- Victor Chan
- Ken Rim
- et al.
- 2005
- CICC 2005