Investigations of silicon nano-crystal floating gate memories
Arvind Kumar, Jeffrey J. Welser, et al.
MRS Spring 2000
At the onset of innovative device structures intended to extend the roadmap for silicon CMOS, many techniques have been investigated to improve carrier mobility in silicon MOSFETs. A novel planar silicon CMOS structure, seeking optimized surface orientation, and hence carrier mobilities for both nFETs and pFETs, emerged. Hybrid-orientation technology provides nFETs on (100) surface orientation and pFETs on (110) surface orientation through wafer bonding and silicon selective epitaxy. The fabrication processes and device characteristics are reviewed in this paper. © 2006 IEEE.
Arvind Kumar, Jeffrey J. Welser, et al.
MRS Spring 2000
Benjamin G. Lee, Clint L. Schow, et al.
Journal of Lightwave Technology
Meikei Ieong, Leland Chang, et al.
ICICDT 2005
Jeremy D. Schaub, Steven J. Koester, et al.
SPIE IOPTO 2004