A Methodology to Optimize the Number and Placement of Decoupling Capacitors in a Multilevel Power Delivery Network
- Ram Krishna
- Thong Nguyen
- et al.
- 2022
- EDAPS 2022
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48 results for Arvind Kumar
Advanced modeling and optimization of high performance 32nm HKMG SOI CMOS for RF/analog SoC applications
- Sungjae Lee
- J. Johnson
- et al.
- 2012
- VLSI Technology 2012
A Simple, unified 3D stress model for device design in stress-enhanced mobility technologies
- Arvind Kumar
- Kai Xiu
- et al.
- 2012
- SISPAD 2012
Sub-25nm FinFET with advanced fin formation and short channel effect engineering
- Tenko Yamashita
- Veeraraghvan S. Basker
- et al.
- 2011
- VLSI Technology 2011
ETSOI CMOS for system-on-chip applications featuring 22nm gate length, sub-100nm gate pitch, and 0.08μm2 SRAM cell
- Kangguo Cheng
- A. Khakifirooz
- et al.
- 2011
- VLSI Technology 2011
ETSOI CMOS for system-on-chip applications featuring 22nm gate length, sub-100nm gate pitch, and 0.08μm2 SRAM cell
- Kangguo Cheng
- A. Khakifirooz
- et al.
- 2011
- VLSI Circuits 2011
Impact of back bias on ultra-thin body and BOX (UTBB) devices
- Q. Liu
- Frederic Monsieur
- et al.
- 2011
- VLSI Technology 2011
Ultra-thin Body and BOX (UTBB) device for aggressive scaling of CMOS technology
- Q. Liu
- A. Yagishita
- et al.
- 2011
- CSTIC 2011
FDSOI CMOS with dual backgate control for performance and power modulation
- Jeng-Bang Yau
- Jin Cai
- et al.
- 2009
- VLSI-TSA 2009
FinFET resistance mitigation through design and process optimization
- Cindy Wang
- Josephine Chang
- et al.
- 2009
- VLSI-TSA 2009