Floating-body concerns for SOI dynamic random access memory (DRAM)
- J.A. Mandelman
- J. Barth
- et al.
- 1996
- IEEE International SOI Conference 1996
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24 results for J. DeBrosse
Flexible test mode design for DRAM characterization
- H. Wong
- T. Kirihata
- et al.
- 1996
- VLSI Circuits 1996
Feasibility of an active-read approach for spin-torque switched magnetic tunnel junctions in a random access memory
- Jonathan Z. Sun
- John Debrosse
- et al.
- 2013
- Journal of Applied Physics
A study of write margin of spin torque transfer magnetic random access memory technology
- Tai Min
- Qiang Chen
- et al.
- 2010
- IEEE Transactions on Magnetics
Design considerations for MRAM
- Thomas M. Maffitt
- John K. DeBrosse
- et al.
- 2006
- IBM J. Res. Dev
A 16-Mb MR AM featuring bootstrapped write drivers
- Dietmar Gogl
- Christian Arndt
- et al.
- 2005
- IEEE Journal of Solid-State Circuits
A High-Speed 128-kb MRAM Core for Future Universal Memory Applications
- John DeBrosse
- Dietmar Gogl
- et al.
- 2004
- IEEE Journal of Solid-State Circuits
Challenges and future directions for the scaling of dynamic random-access memory (DRAM)
- Jack A. Mandelman
- Robert H. Dennard
- et al.
- 2002
- IBM J. Res. Dev
A 7F2 cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4-Gb DRAM's
- Heinz Hoenigschmid
- Alexander Frey
- et al.
- 2000
- IEEE Journal of Solid-State Circuits
A 220-mm2, four- and eight-bank, 256-Mb SDRAM with single-sided stitched WL architecture
- Toshiaki Kirihata
- Martin Gall
- et al.
- 1998
- IEEE Journal of Solid-State Circuits