A 0.039um2 high performance eDRAM cell based on 32nm high-K/metal SOI technology
- Nauman Z. Butt
- Kevin McStay
- et al.
- 2010
- IEDM 2010
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13 results for John Barth
A 500MHz random cycle 1.5ns-latency, SOI embedded DRAM macro featuring a 3T micro sense amplifier
- John Barth
- William Reohr
- et al.
- 2007
- ISSCC 2007
A 0.127 μm2 high performance 65 nm SOI based embedded DRAM for on-processor applications
- G. Wang
- K. Cheng
- et al.
- 2006
- IEDM 2006
Isolated Preset Architecture for a 32nm SOI embedded DRAM macro
- John Barth
- Don Plass
- et al.
- 2012
- VLSI Circuits 2012
Performance analysis and modeling of deep trench decoupling capacitor for 32 nm high-performance SOI processors and beyond
- Balaji Jayaraman
- Sneha Gupta
- et al.
- 2012
- ICICDT 2012
Process-design considerations for three dimensional memory integration
- S.S. Iyer
- T. Kirihata
- et al.
- 2009
- VLSI Technology 2009
An on-chip dual supply charge pump system for 45nm PD SOI eDRAM
- J.B. Kuang
- A. Mathews
- et al.
- 2008
- ESSCIRC 2008
A one MB cache subsystem prototype with 2GHz embedded DRAMs in 45nm SOI CMOS
- Peter Klim
- John Barth
- et al.
- 2008
- VLSI Circuits 2008
Floating-body concerns for SOI dynamic random access memory (DRAM)
- J.A. Mandelman
- J. Barth
- et al.
- 1996
- IEEE International SOI Conference 1996
IBM POWER7 processor circuit design
- Dieter Wendel
- John Barth
- et al.
- 2011
- IBM J. Res. Dev