A 45nm low cost low power platform by using integrated dual-stress-liner technology
- J. Yuan
- S.S. Tan
- et al.
- 2006
- VLSI Technology 2006
Publications
Date
Featured collections
Popular topics
58 results for Terence B. Hook
Evaluation of device damage from e-beam curing of ultra low-k BEOL dielectrics
- S. Mehta
- C. Dimitrakopoulos
- et al.
- 2005
- AMC 2005
Interface state generation in pFETs with ultra-thin oxide and oxynitride on (100) and (110) Si substrates
- J.H. Stathis
- R. Bolam
- et al.
- 2005
- INFOS 2005
High performance and low power transistors integrated in 65nm bulk CMOS technology
- Z. Luo
- A. Steegen
- et al.
- 2004
- IEDM 2004
Enhanced multi-threshold (MTCMOS) circuits using variable well bias
- S.V. Kosonocky
- M.J. Immediato
- et al.
- 2001
- ISLPED 2001
Controlling and plasma- and process- induced damage
- T.B. Hook
- 2001
- Semiconductor International
The combined effects of deuterium anneals and deuterated barrier-nitride processing on hot-electron degradation in MOSFET's
- Thomas G. Ference
- Jay S. Burnham
- et al.
- 1999
- IEEE Transactions on Electron Devices
A high-performance 0.5-μm BiCMOS technology with 3.3-V CMOS devices
- Eric D. Johnson
- T.B. Hook
- et al.
- 1990
- VLSI Technology 1990