Effects of trap-assisted tunneling on gate-induced drain leakage in silicon-germanium channel p-type FET for scaled supply voltages
- Vishal A. Tiwari
- Rama Divakaruni
- et al.
- 2016
- Japanese Journal of Applied Physics
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58 results for Terence B. Hook
Vertical Slit FET at 7-nm Node and beyond
- Ping-Lin Yang
- Terence B. Hook
- et al.
- 2016
- IEEE T-ED
Transistor Matching and Fin Angle Variation in FinFET Technology
- Samarth Agarwal
- Terence B. Hook
- et al.
- 2015
- IEEE T-ED
Super fast physics-based methodology for accurate memory yield prediction
- Rajiv V. Joshi
- Keunwoo Kim
- et al.
- 2015
- IEEE Transactions on VLSI Systems
Transistor mismatch properties in deep-submicrometer CMOS technologies
- Xiaobin Yuan
- Takashi Shimizu
- et al.
- 2011
- IEEE T-ED
Gate-induced-drain-leakage current in 45-nm CMOS technology
- Xiaohin Yuan
- Jae-Eun Park
- et al.
- 2008
- IEEE T-DMR
Controlling and plasma- and process- induced damage
- T.B. Hook
- 2001
- Semiconductor International
The combined effects of deuterium anneals and deuterated barrier-nitride processing on hot-electron degradation in MOSFET's
- Thomas G. Ference
- Jay S. Burnham
- et al.
- 1999
- IEEE Transactions on Electron Devices