Training a Probabilistic Graphical Model with Resistive Switching Electronic Synapses
- Sukru Burc Eryilmaz
- Emre Neftci
- et al.
- 2016
- IEEE T-ED
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Lateral InAs/Si p-Type Tunnel FETs Integrated on Si - Part 2: Simulation Study of the Impact of Interface Traps
- Saurabh Sant
- Kirsten E. Moselund
- et al.
- 2016
- IEEE T-ED
Lateral InAs/Si p-Type Tunnel FETs Integrated on Si - Part 1: Experimental Devices
- Kirsten E. Moselund
- D. Cutaia
- et al.
- 2016
- IEEE T-ED
A Phase Change Memory Cell With Metal Nitride Liner as a Resistance Stabilizer to Reduce Read Current Noise for MLC Optimization
- Sangbum Kim
- Norma Sosa
- et al.
- 2016
- IEEE T-ED
Self-Heating Measurement of 14-nm FinFET SOI Transistors Using 2-D Time-Resolved Emission
- Franco Stellari
- Keith A. Jenkins
- et al.
- 2016
- IEEE T-ED
Substrate-voltage modulation of currents in symmetric SOI lateral bipolar transistors
- Jeng-Bang Yau
- Jin Cai
- et al.
- 2016
- IEEE T-ED
The III-nitride double heterostructure revisited: Benefits for threshold voltage engineering of mis devices
- Herwig Hahn
- Carsten Funck
- et al.
- 2016
- IEEE T-ED
Ultrathin Body InGaAs MOSFETs on III-V-On-Insulator Integrated with Silicon Active Substrate (III-V-OIAS)
- Jianqiang Lin
- Lukas Czornomaz
- et al.
- 2016
- IEEE T-ED
Toward ultimate scaling of MOSFET
- Ramachandran Muralidhar
- Isaac Lauer
- et al.
- 2016
- IEEE T-ED
Vertical Slit FET at 7-nm Node and beyond
- Ping-Lin Yang
- Terence B. Hook
- et al.
- 2016
- IEEE T-ED