System-level power consumption modeling and tradeoff analysis techniques for superscalar processor design
- Thomas M. Conte
- Kishore N. Menezes
- et al.
- 2000
- IEEE Transactions on VLSI Systems
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Statistical analysis of timing rules for high-speed synchronous VLSI systems
- Chung-Sheng Li
- Kumar N. Sivarajan
- et al.
- 1999
- IEEE Transactions on VLSI Systems
Peephole optimization of asynchronous macromodule networks
- Ganesh Gopalakrishnan
- Prabhakar Kudva
- et al.
- 1999
- IEEE Transactions on VLSI Systems
Accurate area and delay estimation from RTL descriptions
- Arvind Srinivasan
- Gary D. Huber
- et al.
- 1998
- IEEE Transactions on VLSI Systems
Energy optimization of multilevel cache architectures for RISC and CISC processors
- Uming Ko
- Poras T. Balsara
- et al.
- 1998
- IEEE Transactions on VLSI Systems
Control-flow versus data-flow-based scheduling: Combining both approaches in an adaptive scheduling system
- Reinaldo A. Bergamaschi
- Salil Raje
- et al.
- 1997
- IEEE Transactions on VLSI Systems
Design of a 32 b monolithic microprocessor based on GaAs HMESFET technology
- Chien-Kuo V. Tien
- Kelvin Lewis
- et al.
- 1997
- IEEE Transactions on VLSI Systems
AVPGEN—A Test Generator for Architecture Verification
- A.K. Chandra
- V.S. Iyengar
- et al.
- 1995
- IEEE Transactions on VLSI Systems
Partial Address Directory for Cache Access
- Lishing Liu
- 1994
- IEEE Transactions on VLSI Systems
Diagnosing Scan Chain Faults
- Sandip Kundu
- 1994
- IEEE Transactions on VLSI Systems