Stress proximity technique for performance improvement with dual stress liner at 45nm technology and beyond
- X. Chen
- S. Fang
- et al.
- 2006
- VLSI Technology 2006
Dureseti Chidambarrao
Title
STSM - Thermal & Design-Technology-Manufacturing Solutions
Bio
Dureseti (Chidu) Chidambarrao is a recognized expert in Modeling, semiconductor R&D, Design For Manufacturability, and Design Technology Co-Optimization. Chidu is currently a Senior Technical Staff Member at IBM Research where he leads cross-functional teams in Thermal Solutions for Chiplets and Advance Packaging and device architecture components of the 2nm program. Before joining IBM Research, Chidu worked at IBM Infrastructure where he led the Product-Technology-Interactions team to help deliver P/Z chips for IBM’s mainframes for the 14, 7, and 5nm technology nodes. He developed his deep process, device, and DTCO expertise while at the IBM Semiconductor R&D Center working on the 90nm through 22nm CMOS nodes. Chidu’s technical accomplishments have been recognized with multiple awards internally at IBM, including a Corporate Award in 2022, IBM’s highest technical recognition.
Chidu has over 225 US patents, is an IBM Master Inventor for 15 years, and has 65 publications. Chidu got his B Tech from the Indian Institute of Technology, Madras and his PhD from North Carolina State University.
Publications
Effect of tensile uniaxial stress on the electron transport properties of deeply scaled FD-SOI n-type MOSFETs
- H. Nayfeh
- D. Singh
- et al.
- 2006
- IEEE Electron Device Letters
High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell
- E. Leobandung
- H. Nayakama
- et al.
- 2005
- VLSI Technology 2005
Integration and optimization of embedded-SiGe, compressive and tensile stressed liner films, and stress memorization in advanced SOI CMOS technologies
- M. Horstmann
- A. Wei
- et al.
- 2005
- IEDM 2005
Stress memorization in high-performance FDSOI devices with ultra-thin silicon channels and 25nm gate lengths
- D. Singh
- J. Sleight
- et al.
- 2005
- IEDM 2005
Design of high performance PFETs with strained Si channel and laser anneal
- Z. Luo
- Y.F. Chong
- et al.
- 2005
- IEDM 2005
High performance 65 nm SOI technology with enhanced transistor strain and advanced-low-K BEOL
- W.-H. Lee
- A. Waite
- et al.
- 2005
- IEDM 2005
Effect of contact liner stress in high-performance FDSOI devices with ultra-thin silicon channels and 30 nm gate lengths
- D. Singh
- J. Hergenrother
- et al.
- 2005
- IEEE International SOI Conference 2005
Dual stress liner enhancement in hybrid orientation technology
- C. Sheraw
- M. Yang
- et al.
- 2005
- VLSI Technology 2005
Controlled nucleation of dislocations by a spatially localized stress field
- M. Kammler
- D. Chidambarrao
- et al.
- 2005
- Applied Physics Letters
Patents
- US
- 11960830
- US
- 11308257
- US
- 11303285
- US
- 10839133
- US
- 10628544
- US
- 10614190
- US
- 10592627
- DE
- 112012000310.1
- CN
- ZL201280010634.4
- US
- 9646124
Top collaborators
RB
Ramon Bertran Monfort
Senior Research Scientist @ Efficient and Resilient Systems Research Group
AB
Alper Buyuktosunoglu
Principal Research Scientist
HN
Hasan M Nayfeh
Senior Research Engineer, Quantum Computing
VN
Vijay Narayanan
IBM Fellow & Strategist, Physics of AI. Senior Manager, PCM and AI Materials