Block-Level Design Optimization for Sub-100-nm Cell Height Libraries with Stacked Transistor
- Nick Lanzillo
- Jim Mazza
- et al.
- 2025
- IEDM 2025
Kang-ill Seo is a Project Lead at IBM, driving research in Chiplet and Advanced Packaging for high-performance computing and AI hardware. His current work focuses on 2.5D and 3D integration, Co-Packaged Optics for high-bandwidth communication, and System-Technology Co-Optimization (STCO), including advanced thermal management solutions.
Prior to joining IBM, Dr. Seo served as Vice President at Samsung Electronics, where he led advanced logic technology R&D for low-power and high-performance computing. He spearheaded the Pathfinding joint project between Samsung and IBM Research in Albany, NY, contributing to groundbreaking innovations such as FinFET, Nanosheet, and Stacked Nanosheet devices, as well as novel interconnect technologies like Cu scaling, subtractive Ru, and DTCO strategies to extend Moore’s Law. During his tenure, he played a key role in developing multiple generations of logic technologies from 20nm to 7nm. His contributions earned him numerous honors, including the Most Outstanding Research Award from the CEO of Samsung Electronics and the National Outstanding Research Award in R&D from the President of Korea.
Dr. Seo holds an M.S. and Ph.D. in Electrical Engineering and Materials Science & Engineering from Stanford University (2025 and 2026). His research has resulted in 30 peer-reviewed publications and over 100 issued patents. He has been an active member of the IEDM Executive Committee since 2018.