Efficient Pipelined Execution of CNNs Based on In-Memory Computing and Graph Homomorphism Verification
- Martino Dazzi
- Abu Sebastian
- et al.
- 2021
- IEEE TC
Bio
Pier Andrea Francese received the Laurea degree in electrical engineering (cum laude) from the Politecnico di Milano, Italy, and the Ph.D. degree from the Federal Institute of Technology of Zurich (ETH), Switzerland, in 1993 and 2005, respectively. He is currently a Principal Research Staff Member at the IBM Zurich Research Laboratory in Rueschlikon, Switzerland, and he serves as the Technical Leader of the high-speed interconnect technology group. His research interests are in the areas of high-speed data converters, analog equalization and clock-data-recovery circuit techniques for wireline and optical transceivers and, more recently, in analog signal processing for in-memory and quantum computing.
Publications
Experimental efficiency evaluation of stacked transistor half-bridge topologies in 14 nm cmos technology
- Pedro André Martins Bezerra
- Florian Krismer
- et al.
- 2021
- Electronics (Switzerland)
An 8b DAC-Based SST TX Using Metal Gate Resistors with 1.4pJ/b Efficiency at 112Gb/s PAM-4 and 8-Tap FFE in 7iim CMOS
- Marcel Kossel
- Vishal Khatri
- et al.
- 2021
- ISSCC 2021
An SRAM-Based Multibit In-Memory Matrix-Vector Multiplier with a Precision That Scales Linearly in Area, Time, and Power
- Riduan Khaddam-Aljameh
- Pier Andrea Francese
- et al.
- 2021
- IEEE Transactions on VLSI Systems
A 25-50Gb/s 2.22pJ/b NRZ RX with Dual-Bank and 3-tap Speculative DFE for Microprocessor Application in 7nm FinFET CMOS
- Yang You
- Glen Wiedemeier
- et al.
- 2020
- VLSI Circuits 2020
An In-Comparator Aperture-Time Equalization in a 7-nm FinFET CMOS 40-Gb/s Receiver
- Abdullah Serdar Yonar
- Pier Andrea Francese
- et al.
- 2020
- IEEE SSC-L
A 161-mW 56-Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14-nm FinFET
- Gain Kim
- Marcel Kossel
- et al.
- 2020
- IEEE JSSC
A 4.8pJ/b 56Gb/s ADC-Based PAM-4 Wireline Receiver Data-Path with Cyclic Prefix in 14nm FinFET
- Gain Kim
- Lukas Kull
- et al.
- 2019
- A-SSCC 2019
Deep learning acceleration based on in-memory computing
- Evangelos Eleftheriou
- Geethan Karunaratne
- et al.
- 2019
- IBM J. Res. Dev
BBPD with wide input phase range
- Marcel Kossel
- Pier Andrea Francese
- et al.
- 2019
- Electronics Letters
Patents
- US
- 12095473
- US
- 12088316
- DE
- 11 2019 000 181
- TW
- I850965
- GB
- 2620314
- KR
- 2672586
- CN
- ZL201980010119.8
- SG
- 11202110345X
- US
- 11916568
- JP
- 7427030
Projects
High-Speed I/O Links
Designing the next generation High-Speed I/O Links targeting low power consumption, low latency and small silicon area.
Top collaborators
MB
Matthias Brändli
Digital Circuit Design
TM
Thomas Morf
Senior Research Scientist
MK
Marcel Kossel
Circuit Designer
VC
Victor Chan
Yield learning & Diag Eng Prof