A 35mW8 b 8.8 GS/s SAR ADC with low-power capacitive reference buffers in 32nm Digital SOI CMOS
- Lukas Kull
- Thomas Toifl
- et al.
- 2013
- VLSI Circuits 2013
Pier Andrea Francese received the Laurea degree in electrical engineering (cum laude) from the Politecnico di Milano, Italy, and the Ph.D. degree from the Federal Institute of Technology of Zurich (ETH), Switzerland, in 1993 and 2005, respectively. He is currently a Principal Research Staff Member at the IBM Zurich Research Laboratory in Rueschlikon, Switzerland, and he serves as the Technical Leader of the high-speed interconnect technology group. His research interests are in the areas of high-speed data converters, analog equalization and clock-data-recovery circuit techniques for wireline and optical transceivers and, more recently, in analog signal processing for in-memory and quantum computing.