A DDR3/4 memory link TX supporting 24-40 ω, 0.8-1.6 V, 0.8-5.0 Gb/s with slew rate control and thin oxide output stages in 22-nm CMOS SOI
- Marcel Kossel
- Christian Menolfi
- et al.
- 2014
- ESSCIRC 2014
Pier Andrea Francese
Title
Principal RSM - Analog Circuit Design
Bio
Pier Andrea Francese received the Laurea degree in electrical engineering (cum laude) from the Politecnico di Milano, Italy, and the Ph.D. degree from the Federal Institute of Technology of Zurich (ETH), Switzerland, in 1993 and 2005, respectively. He is currently a Principal Research Staff Member at the IBM Zurich Research Laboratory in Rueschlikon, Switzerland, and he serves as the Technical Leader of the high-speed interconnect technology group. His research interests are in the areas of high-speed data converters, analog equalization and clock-data-recovery circuit techniques for wireline and optical transceivers and, more recently, in analog signal processing for in-memory and quantum computing.
Publications
A 16 Gb/s receiver with DC wander compensated rail-to-rail AC coupling and passive linear-equalizer in 22 nm CMOS
- Pier Andrea Francese
- Thomas Toifl
- et al.
- 2014
- ESSCIRC 2014
A 3.5pJ/bit 8-tap-feed-forward 8-tap-decision feedback digital equalizer for 16Gb/s I/Os
- Thomas Toifl
- Peter Buchmann
- et al.
- 2014
- ESSCIRC 2014
Wide bandwidth room-temperature THz imaging array based on antenna-coupled MOSFET bolometer
- Thomas Morf
- Bernhard Klein
- et al.
- 2014
- Sensors and Actuators, A: Physical
A deep trench capacitor based 2:1 and 3:2 reconfigurable on-chip switched capacitor DC-DC converter in 32 nm SOI CMOS
- Toke M. Andersen
- Florian Krismer
- et al.
- 2014
- APEC 2014
A 90GS/s 8b 667mW 64× interleaved SAR ADC in 32nm digital SOI CMOS
- Lukas Kull
- Thomas Toifl
- et al.
- 2014
- ISSCC 2014
A sub-ns response on-chip switched-capacitor DC-DC voltage regulator delivering 3.7W/mm2 at 90% efficiency using deep-trench capacitors in 32nm SOI CMOS
- Toke Meyer Andersen
- Florian Krismer
- et al.
- 2014
- ISSCC 2014
A 3.1 mW 8b 1.2 GS/s single-Channel asynchronous SAR ADC with alternate comparators for enhanced speed in 32 nm digital SOI CMOS
- Lukas Kull
- Thomas Toifl
- et al.
- 2013
- IEEE JSSC
A 10 Gb/s 8-tap 6b 2-PAM/4-PAM tomlinson-harashima precoding transmitter for future memory-link applications in 22-nm SOI CMOS
- Marcel Kossel
- Thomas Toifl
- et al.
- 2013
- IEEE JSSC
A 16Gb/s 3.7mW/Gb/s 8-tap DFE receiver and baud rate CDR with 30kppm tracking bandwidth
- Pier Andrea Francese
- Thomas Toifl
- et al.
- 2013
- A-SSCC 2013
Patents
- US
- 12095473
- US
- 12088316
- DE
- 11 2019 000 181
- TW
- I850965
- GB
- 2620314
- KR
- 2672586
- CN
- ZL201980010119.8
- SG
- 11202110345X
- US
- 11916568
- JP
- 7427030
Projects
High-Speed I/O Links
Designing the next generation High-Speed I/O Links targeting low power consumption, low latency and small silicon area.
Top collaborators
MB
Matthias Brändli
Digital Circuit Design
MK
Marcel Kossel
Circuit Designer
TM
Thomas Morf
Senior Research Scientist
CZ
Cezar Zota
Staff Research Scientist, Master inventor