Gate-induced-drain-leakage current in 45-nm CMOS technology
- Xiaohin Yuan
- Jae-Eun Park
- et al.
- 2008
- IEEE T-DMR
Bio
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Current / Recent: STSM in Yield / characterization of 2nm Nanosheet Logic; Analog AI hardware and chiplet technologies.
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Working in semiconductor industry over 20 years in IBM.
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Technical leadership in FEOL integration and device teams of CMOS 90 to deep sub-micron in bulk / SOI technologies, innovative and inventive delivery of process technologies from concept to qualification to manufacturing.
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Specialties include semiconductor device & integration in R&D and production, product - customer deployment, technology licensing and technical support. Extensive experience in running lots and characterization of device / inline-metrology / PLY / Health-of-line and yield data. Device, SRAM and product yield learning and improvement through Hands-on data analysis.
Publications
High performance transistors featured in an aggressively scaled 45nm bulk CMOS technology
- Z. Luo
- N. Rovedo
- et al.
- 2007
- VLSI Technology 2007
Characterization and analysis of gate-induced-drain-leakage current in 45 nm CMOS technology
- Xiaobin Yuan
- Jae-Eun Park
- et al.
- 2007
- IIRW 2007
Uniaxial strain relaxation on ultra-thin strained-Si directly on insulator (SSDOI) substrates
- Haizhou Yin
- Z. Ren
- et al.
- 2006
- ICSICT 2006
Direct silicon bonded (DSB) substrate solid phase epitaxy (SPE) integration scheme study for high performance bulk CMOS
- Haizhou Yin
- C.Y. Sung
- et al.
- 2006
- IEDM 2006
Integration of local stress techniques with strained-Si directly on insulator (SSDOI) substrates
- Haizhou Yin
- Z. Ren
- et al.
- 2006
- VLSI Technology 2006
Process induced stress for CMOS performance improvement
- S. Fang
- S.S. Tan
- et al.
- 2006
- ICSICT 2006
Transistor scaling with novel materials
- Meikei Ieong
- Vijay Narayanan
- et al.
- 2006
- Materials Today
Hybrid-orientation technology (HOT): Opportunities and challenges
- Min Yang
- Victor W.C. Chan
- et al.
- 2006
- IEEE Transactions on Electron Devices
High performance CMOS bulk technology using direct silicon bond (DSB) mixed crystal orientation substrates
- Chun-Yung Sung
- Haizhou Yin
- et al.
- 2005
- IEDM 2005
Patents
- US
- 11309221
- US
- 11257716
- US
- 11222820
- US
- 10985076
- US
- 10943990
- US
- 10229984
- US
- 10043744
- US
- 9935174
- US
- 9929250
- US
- 9837351
Top collaborators
IA
Ishtiaq Ahsan
Senior Manager, Yield/ Test & Characterization, IBM Semiconductor Technology Research & Development
VN
Vijay Narayanan
IBM Fellow & Strategist, Physics of AI. Senior Manager, PCM and AI Materials
GB
Geoffrey Burr
Distinguished RSM