A 16-Mb MR AM featuring bootstrapped write drivers

A 16-Mb magnetic random access memory (MRAM) is demonstrated in 0.18-νm three-Cu-level CMOS with a three-level MRAM process adder. The chip, the highest density MRAM reported to date, utilizes a 1.42 μm≥2∼ 1-transistor 1-magnetic tunnel junction (1T1MTJ) cell, measures 79 mm2 and features a & 16 asynchronous SRAM-like interface. The paper describes the cell, architecture, and circuit techniques unique to multi-Mb MRAM design, including a novel bootstrapped write driver circuit. Hardware results are presented. © 2005 IEEE.