Conference paperA one MB cache subsystem prototype with 2GHz embedded DRAMs in 45nm SOI CMOSPeter Klim, John Barth, et al.VLSI Circuits 2008
Conference paperNew tools and methodology for advanced parametric and defect structure testRaphael Robertazzi, Louis Medina, et al.IEEE ITC 2010
Conference paperA 500MHz random cycle 1.5ns-latency, SOI embedded DRAM macro featuring a 3T micro sense amplifierJohn Barth, William Reohr, et al.ISSCC 2007
Conference paperA Cryo-CMOS Transmon Qubit Controller and Verification with FPGA EmulationKevin Tien, Ken Inoue, et al.DATE 2022
