A systematic study of temperature, polarity, thickness, and ramp rate dependencies of ramp-voltage stress for SiO2 and its comparison with 2D gate dielectrics

A systematic ramp voltage stress (RVS) study of temperature (30°C to 200°C), polarity, and ramp rate (10V/s and 0.0002V/s) has been carried out over a wide range of $SiO_2$ thickness (2-12nm). Low activation energy (ΔH0.01eV) was observed compared to constant voltage stress results (ΔH~0.5eV). We resolve these ΔH differences by reporting a new temperature dependence of power-law voltage-acceleration exponents for FN to DT regimes. Extensive $SiO_2$ VBD data is given for comparison to other dielectrics.