A 14 nm embedded STT-MRAM CMOS technology
- Daniel C. Edelstein
- M. Rizzolo
- et al.
- 2020
- IEDM 2020
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45 results for Richard G. Southwick
First Experimental Demonstration of MRAM Data Scrubbing: 80 Mb MRAM with 40 nm junctions for Last Level Cache Applications
- H. Wu
- V. Katragadda
- et al.
- 2021
- IEDM 2021
Multiphonon-electron coupling enhanced defect generation and breakdown mechanism in MOL new spacer dielectrics for 7nm/5nm technology nodes and beyond
- Ernest Wu
- Richard G. Southwick
- et al.
- 2020
- IEDM 2020
Toward High Performance SiGe Channel CMOS: Design of High Electron Mobility in SiGe nFinFETs Outperforming Si
- Choonghyun Lee
- Richard G. Southwick
- et al.
- 2018
- IEDM 2018
A comparative study of strain and Ge content in Si1-xGex channel using planar FETs, FinFETs, and strained relaxed buffer layer FinFETs
- Choonghyun Lee
- Shogo Mochizuki
- et al.
- 2017
- IEDM 2017
Modeling of NBTI time kinetics and T dependence of VAF in SiGe p-FinFETs
- Narendra Parihar
- Richard G. Southwick
- et al.
- 2017
- IEDM 2017
Fundamental limitations of existing models and future solutions for dielectric reliability and RRAM applications (invited)
- Ernest Y. Wu
- Andrew Kim
- et al.
- 2017
- IEDM 2017
Hot carrier effect in ultra-scaled replacement metal gate Sii-xGex channel p-FinFETs
- Miaomiao Wang
- X. Miao
- et al.
- 2016
- IEDM 2016
Engineering the electronic defect bands at the Si1-xGex/IL interface: Approaching the intrinsic carrier transport in compressively-strained Si1-xGex pFETs
- Choonghyun Lee
- Richard G. Southwick
- et al.
- 2016
- IEDM 2016
A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels
- Ruilong Xie
- Pietro Montanini
- et al.
- 2016
- IEDM 2016