Approach to pattern aspect ratio control

Abstract

Many semiconductor chip designs require precise simultaneous control of both the width and length of asymmetric features. Line shortening due to optical, resist processing, and mask effects cause the process windows for width and length to diverge. Typically differential mask biasing has been used to maximize the common process window for both axes. As we enter the gigabit era limitations in grid size and mask write times may become significant restrictions to meeting required device tolerances with that approach. Simulations of aerial image and resist processing using SPLAT and LEOPOLD indicate that for a given mask there is considerable latitude to adjust the length of features without a significant loss of process window. An experimental design matrix was used to verify the simulation results and develop a regression model of pupil fill, numerical aperture, and resist diffusion effects. This model was then applied to optimize the processing conditions for several product masks. This technique is particularly useful early in the development cycle when mask to mask repeatability is poor and lead times are long. It may also be used to fine tune image sizes in manufacturing.