As-Se-Ge-S and Ge-N Heterostructures for Superior OTS Performance

Abstract

This study presents a scaling analysis of ovonic threshold switching (OTS) multilayered heterostructures (HS) for use in storage class memory (SCM) applications. HS selectors were created with repeating layers of AsSeGeS and GeN, varying interlayer thickness ratios and the number of interfaces to explore the contribution of layers thickness and interfacial barrier on device performance. Raman spectroscopy indicated distinct bonding preferences and showed reduced interlayer mixing associated with thicker GeN layers. Thicker GeN layers also led to a more significant threshold voltage $(V_th)$ increase, compared to the $V_{th}$ gain from interfacial barrier effects. It was also found that an increased thickness ratio of AsSeGeS to GeN improved off currents $(I_{off})$. All HS demonstrated significant cycling stability and endurance improvements up to $10^{11}$ cycles. Compared to a bulk device, an optimized 15nm HS showed a four order of magnitude lower $I_{off}$, a 1V larger $V_{th}$, and improved $I_{off}$ cycling stability.