Robert W. Keyes
Physical Review B
Conference paper
Circuit implications of gate oxide breakdown
Abstract
A model for the oxide breakdown (BD) current-voltage (I-V) characteristics has been experimentally verified on CMOS inverters. The implications of oxide BD on the performance of various CMOS circuit elements are discussed. Examples are shown of cell stability and bitline differentials in static memory (SRAM), signal timing, and inverter chains. © 2003 Elsevier Ltd. All rights reserved.
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