Éamon O'Connor, Mattia Halter, et al.
APL Materials
We report the first RF characterization of short-channel replacement metal gate (RMG) InGaAs-OI nFETs built in a 3D Monolithic (3DM) CMOS process. This process features RMG InGaAs-OI nFET top layer and SiGe-OI fin pFET bottom layer. We demonstrate state-of-The-Art device integration on both levels. The bottom layer SiGe-OI pFETs are fabricated with a Gate-First (GF) process with fins scaled down to ∼15 nm width and featuring epitaxial raised source drain (RSD) and silicide. The top layer InGaAs nFETs are fabricated with a RMG process featuring a self-Aligned epitaxial raised source drain (RSD). We show that the 3D monolithic integration scheme does not degrade the performance of the bottom SiGe-OI pFETs owing to an optimized thermal budget for the top InGaAs nFETs. From the RF characterizations performed (post-3D monolithic process) on multifinger-gate InGaAs-OI nFETs, we extract a cut-off frequency (Ft) of 16.4 GHz at a gate-length (Lg) of 120 nm. Measurements on various gate lengths shows increasing cut-off frequency with decreasing gate-length.
Éamon O'Connor, Mattia Halter, et al.
APL Materials
V. Djara, Marilyne Sousa, et al.
Microelectronic Engineering
Veeresh Deshpande, Herwig Hahn, et al.
VLSI Technology 2017
Lukas Czornomaz, Veeresh Deshpande, et al.
ECS Meeting 2017 - New Orleans