Z. Luo, A. Steegen, et al.
IEDM 2004
The root cause for the increase in the TDDB voltage acceleration with decreasing stress voltage in metal gate/high-k n-channel FETs is investigated. Using DC and AC stress methodologies, the effect could be linked to charge trapping in the high-k gate dielectric. Furthermore, a correction for charge trapping is proposed, which results in a single power law voltage dependence for all stress conditions. © 2010 IEEE.
Z. Luo, A. Steegen, et al.
IEDM 2004
Sufi Zafar, A. Kerber, et al.
VLSI Technology 2014
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IRPS 2010
D.P. Ioannou, E. Cartier, et al.
IRPS 2010