Conference paper
NanoStack Transistor Architecture for CMOS 7A Node and Beyond
S. Reboh, C. Zhang, et al.
VLSI Technology and Circuits 2025
Spiral, multilevel spiral, and lateral solenoidal inductor structures are fabricated on silicon substrates using a Cu-damascene VLSI interconnect technology with a 4 μm-thick Cu top layer. Some chips are mounted on quartz substrates to suppress substrate losses. An 80-nH, 16-turn spiral inductor on quartz has a Q of 20, the highest recorded value to date for an integrated inductor of this size.
S. Reboh, C. Zhang, et al.
VLSI Technology and Circuits 2025
F. Chen, J. Gill, et al.
IRPS 2004
D. Edelstein, R.B. Romney, et al.
Review of Scientific Instruments
Chih-Chao Yang, Fen Chen, et al.
IITC 2012