Analyzing path delays for accelerated testing of logic chips
Emily Ray, Barry P. Linder, et al.
IRPS 2015
Hard breakdown (HBD) is shown to be a gradual process with the gate current increasing at a predictable rate exponentially dependent on the instantaneous stress voltage and oxide thickness. This is contrary to conventional wisdom that maintains that HBD is a fast thermally driven process. The HBD degradation rate (DR) for a 15 Å oxide scales from > 1 mA/s at 4 V to < 1 nA/s at 2 V, extrapolating to < 10 fA/s at use voltage. Adding the HBD evolution time to the standard time-to-breakdown potentially reduces the projected fail rate of gate dielectrics by orders of magnitude.
Emily Ray, Barry P. Linder, et al.
IRPS 2015
Miaomiao Wang, Sufi Zafar, et al.
Microelectronic Engineering
Miaomiao Wang, Zuoguang Liu, et al.
IRPS 2015
James H. Stathis
IPFA 2005