Performance enhancement on sub-70 nm strained silicon SOI MOSFETS on ultra-thin thermally mixed strained silicon/SiGe on insulator(TM-SGOI) substrate with raised S/D
- B.H. Lee
- A.C. Mocuta
- et al.
- 2002
- IEDM 2002
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236 results for Keith A. Jenkins
Characteristics and device design of sub-100 nm strained Si N- and PMOSFETs
- K. Rim
- J.O. Chu
- et al.
- 2002
- VLSI Technology 2002
Fully-depleted-collector polysilicon-emitter SiGe-base vertical bipolar transistor on SOI
- Jin Cai
- A. Ajmera
- et al.
- 2002
- VLSI Technology 2002
Measurement of the effect of self-heating in strained-silicon MOSFETs
- Keith A. Jenkins
- K. Rim
- 2002
- IEEE Electron Device Letters
Effective crosstalk isolation through p+ Si substrates with semi-insulating porous Si
- Han-Su Kim
- Keith A. Jenkins
- et al.
- 2002
- IEEE Electron Device Letters
The clock distribution of the power4 microprocessor
- Phillip J. Restle
- Craig A. Carter
- et al.
- 2002
- ISSCC 2002
The clock distribution of the Power4 microprocessor
- Phillip J. Restle
- Craig A. Carter
- et al.
- 2002
- Digest of Technical Papers-IEEE International Solid-State Circuits Conference
A Faraday cage isolation structure for substrate crosstalk suppression
- Joyce H. Wu
- Jörg Scholvin
- et al.
- 2001
- IEEE MWCL
Measurement of history effect in PD/SOI single-ended CPL circuit
- Keith A. Jenkins
- R. Puri
- et al.
- 2001
- IEEE International SOI Conference 2001
A clock distribution network for microprocessors
- Phillip J. Restle
- Timothy G. McNamara
- et al.
- 2001
- IEEE Journal of Solid-State Circuits