Characteristics and device design of sub-100 nm strained Si N- and PMOSFETs

Abstract

The device design and characteristics of sub-100 nm strained Si N- and PMOSFETs were discussed. A enhancement of 110% was observed in the strained Si devices with 1.2% tensile strain, along with a 45% increase in the peak hole mobility. A comparison of current-voltage characteristics of 100 nm PFETs was done. The strained Si (SS) PFETs showed comparable subthreshold characteristics while showing higher current drive.