Parasitic Resistance Reduction Strategies for Advanced CMOS FinFETs beyond 7nm
- Heng Wu
- Oleg Gluschenkov
- et al.
- 2018
- IEDM 2018
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17 results for Zuoguang Liu
Integrated dual SPE processes with low contact resistivity for future CMOS technologies
- Heng Wu
- Soon-Cheon Seo
- et al.
- 2017
- IEDM 2017
Technology viable DC performance elements for Si/SiGe channel CMOS FinFTT
- G. Tsutsui
- Ruqiang Bao
- et al.
- 2016
- IEDM 2016
FinFET performance with Si:P and Ge:Group-III-Metal metastable contact trench alloys
- Oleg Gluschenkov
- Zuoguang Liu
- et al.
- 2016
- IEDM 2016
A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels
- Ruilong Xie
- Pietro Montanini
- et al.
- 2016
- IEDM 2016
Air spacer for 10nm FinFET CMOS and beyond
- K. Cheng
- C. Park
- et al.
- 2016
- IEDM 2016
Sub-10-9 Ω-cm2 n-Type Contact Resistivity for FinFET Technology
- Hiroaki Niimi
- Zuoguang Liu
- et al.
- 2016
- IEEE Electron Device Letters
Parasitic Resistance Reduction for Aggressively Scaled Stacked Nanosheet Transistors
- Su-Chen Fan
- Ruilong Xie
- et al.
- 2020
- IITC 2020
Improved Air Spacer Co-Integrated with Self-Aligned Contact (SAC) and Contact over Active Gate (COAG) for Highly Scaled CMOS Technology
- Kangguo Cheng
- Chanro Park
- et al.
- 2020
- VLSI Technology 2020
Direct Partition Measurement of Parasitic Resistance Components in Advanced Transistor Architectures
- Zuoguang Liu
- Heng Wu
- et al.
- 2019
- VLSI Technology 2019