Advanced Multi-Vt Enabled by Selective Layer Reductions for 2nm Nanosheet Technology and Beyond
- Ruqiang Bao
- Yusuke Oniki
- et al.
- 2024
- IEDM 2024
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19 results for Anthony Chou
2nd Generation dual-channel optimization with cSiGe for 22nm HP technology and beyond
- C. Ortolland
- Daniel Jaeger
- et al.
- 2013
- IEDM 2013
Chip-level power-performance optimization through thermally-driven across-chip variation (ACV) reduction
- X. Yu
- Oleg Gluschenkov
- et al.
- 2011
- IEDM 2011
High performance 45-nm SOI technology with enhanced strain, porous low-k BEOL, and immersion lithography
- S. Narasimha
- K. Onishi
- et al.
- 2006
- IEDM 2006
Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing
- H.S. Yang
- R. Malik
- et al.
- 2004
- IEDM 2004
High Performance CMOS Fabricated on Hybrid Substrate with Different Crystal Orientations
- M. Yang
- M. Ieong
- et al.
- 2003
- IEDM 2003
A high performance 90 nm SOI technology with 0.992 μm2 6T-SRAM cell
- Mukesh Khare
- S. Ku
- et al.
- 2002
- IEDM 2002
Performance dependence of CMOS on silicon substrate orientation for ultrathin oxynitride and HfO2 gate dielectrics
- Min Yang
- Evgeni P. Gusev
- et al.
- 2003
- IEEE Electron Device Letters
Deposited ALD SiO2 high-k/metal gate interface for high voltage analog and I/O devices on next generation alternative channels and FINFET device structures
- S. Siddiqui
- M.M. Chowdhury
- et al.
- 2013
- ECS Meeting 2013
Experimental analysis and modeling of self heating effect in dielectric isolated planar and fin devices
- S. Lee
- Richard A. Wachnik
- et al.
- 2013
- VLSI Technology 2013