Sharp reduction of contact resistivities by effective schottky barrier lowering with silicides as diffusion sources
- Zhen Zhang
- F. Pagette
- et al.
- 2010
- IEEE Electron Device Letters
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43 results for David P. Klaus
High-κ/metal-gate fully depleted SOI CMOS with single-silicide schottky source/drain with sub-30-nm gate length
- Marwan H. Khater
- Zhen Zhang
- et al.
- 2010
- IEEE Electron Device Letters
Resistivity of copper interconnects at 28 nm pitch and copper cross-sectional area below 100 nm2
- Adam Pyzyna
- Hsinyu Tsai
- et al.
- 2017
- IITC 2017
Resistivity of copper interconnects beyond the 7 nm node
- Adam Pyzyna
- Robert L. Bruce
- et al.
- 2015
- VLSI Technology 2015
Self-aligned line-space pattern customization with directed self-assembly graphoepitaxy at 24nm pitch
- Hsinyu Tsai
- Hiroyuki Miyazoe
- et al.
- 2015
- SPIE Advanced Lithography 2015
Pattern transfer of directed self-assembly (DSA) patterns for CMOS device applications
- Hsin-Yu Tsai
- Hiroyuki Miyazoe
- et al.
- 2013
- SPIE Advanced Lithography 2013
Patterning of CMOS device structures for 40-80nm pitches and beyond
- Sebastian U. Engelmann
- R.M. Martin
- et al.
- 2012
- SPIE Advanced Lithography 2012
Pattern collapse mitigation strategies for EUV Lithography
- Dario L. Goldfarb
- Robert L. Bruce
- et al.
- 2012
- SPIE Advanced Lithography 2012
A 0.021 μm2 trigate SRAM cell with aggressively scaled gate and contact pitch
- Michael A. Guillorn
- Josephine Chang
- et al.
- 2011
- VLSI Technology 2011
Effective schottky barrier lowering for contact resistivity reduction using silicides as diffusion sources
- Zhen Zhang
- F. Pagette
- et al.
- 2010
- VLSI-TSA 2010