Ali Khakifirooz, Kangguo Cheng, et al.
IEEE Electron Device Letters
Schottky source/drain (S/D) MOSFETs hold the promise for low series resistance and extremely abrupt junctions, providing a path for device scaling in conjunction with a low Schottky barrier height (SBH). A S/D junction SBH approaching zero is also needed to achieve a competitive current drive. In this letter, we demonstrate a CMOS process flow that accomplishes a reduction of the S/D SBH for nFET and pFET simultaneously using implants into a common NiPt silicide, followed by a low-temperature anneal (500°C 600 °C). These devices have high-κ/metal gate and fully depleted extremely thin SOI with sub-30-nm gate length. © 2010 IEEE.
Ali Khakifirooz, Kangguo Cheng, et al.
IEEE Electron Device Letters
Jessie Rosenberg, William M. J. Green, et al.
IPC 2013
Yingtao Yu, Si Chen, et al.
IEEE Electron Device Letters
Marco Bellini, John D. Cressler, et al.
BCTM 2007