3.5ns CMOS 64K ECL RAM at 77°K
- S.E. Schuster
- T.I. Chappell
- et al.
- 1988
- VLSI Circuits 1988
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66 results for Phillip Restle
6.2 ns 64Kb CMOS RAM with ECL interfaces
- T.I. Chappell
- S.E. Schuster
- et al.
- 1988
- VLSI Circuits 1988
A high performance liquid-nitrogen CMOS SRAM technology
- J.Y.-C. Sun
- S. Klepner
- et al.
- 1988
- ESSDERC 1988
IBM POWER8 circuit design and energy optimization
- Victor Zyuban
- Joshua Friedrich
- et al.
- 2015
- IBM J. Res. Dev
Subtractive router for tree-driven-grid clocks
- Haifeng Qian
- Phillip J. Restle
- et al.
- 2012
- IEEE TCADIS
POWER7™, a highly parallel, scalable multi-core high end server processor
- Dieter F. Wendel
- Ron Kalla
- et al.
- 2011
- IEEE Journal of Solid-State Circuits
A resonant global clock distribution for the cell broadband engine processor
- Steven C. Chan
- Phillip J. Restle
- et al.
- 2009
- IEEE Journal of Solid-State Circuits
IBM POWER6 microprocessor physical design and design methodology
- Rex Berridge
- Robert M. Averill III
- et al.
- 2007
- IBM J. Res. Dev
Distributed differential oscillators for global clock networks
- Steven C. Chan
- Kenneth L. Shepard
- et al.
- 2006
- IEEE Journal of Solid-State Circuits
Uniform-phase uniform-amplitude resonant-load global clock distributions
- Steven C. Chan
- Kenneth L. Shepard
- et al.
- 2005
- IEEE Journal of Solid-State Circuits