High performance 14nm SOI FinFET CMOS technology with 0.0174μm2 embedded DRAM and 15 levels of Cu metallization
- C.-H.C-H. Lin
- Brian Greene
- et al.
- 2014
- IEDM 2014
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12 results for W.-H. Lee
Chip-level power-performance optimization through thermally-driven across-chip variation (ACV) reduction
- X. Yu
- Oleg Gluschenkov
- et al.
- 2011
- IEDM 2011
High performance 65 nm SOI technology with enhanced transistor strain and advanced-low-K BEOL
- W.-H. Lee
- A. Waite
- et al.
- 2005
- IEDM 2005
Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing
- H.S. Yang
- R. Malik
- et al.
- 2004
- IEDM 2004
A high performance 90 nm SOI technology with 0.992 μm2 6T-SRAM cell
- Mukesh Khare
- S. Ku
- et al.
- 2002
- IEDM 2002
Comparative study of CVD TiN vs. ALD TiN for contact metallization in 32nm node and beyond
- Valli Arunachalam
- Filippos Papadatos
- et al.
- 2010
- ADMETA 2010
Advanced metallization developments for 32-nm node CMOS technology contact architecture
- Doug H. Lee
- Valli Arunachalam
- et al.
- 2009
- ADMETA 2009
Characterization of contact module failure mechanisms for SOI technology using E-beam inspection and in-line TEM
- Xing J. Zhou
- Oliver D. Patterson
- et al.
- 2010
- ASMC 2010
High performance 32nm SOI CMOS with high-k/metal gate and 0.149μm 2 SRAM and ultra low-k back end with eleven levels of copper
- B. Greene
- Q. Liang
- et al.
- 2009
- VLSI Technology 2009
Challenges and issues in 65nm CMOS logic technology
- Woo-Hyeong Lee
- 2007
- ECS Meeting 2007