Publications

This is our catalog of publications authored by IBM researchers, in collaboration with the global research community. It’s an ever-growing body of work that shows why IBM is one of the most important contributors to modern computing.

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69 results for Daniel Friedman

A modular all-digital PLL architecture enabling both 1-to-2GHz and 24-to-32GHz operation in 65NM CMOS
- - A. Rylyakov
  - J. Tierno
  - et al.
- 2008
- ISSCC 2008
A wide power-supply range (0.5V-to-1.3V) wide tuning range (500 MHz-to-8 GHz) all-static CMOS AD PLL in 65nm SOI
- - A. Rylyakov
  - J. Tierno
  - et al.
- 2007
- ISSCC 2007
A 7Gb/s 9.3mW 2-Tap current-integrating DFE receiver
- - Matt Park
  - John Bulzacchelli
  - et al.
- 2007
- ISSCC 2007
All-digital dynamic self-detection and self-compensation of static phase offsets in charge-pump PLLs
- - Liu Yong
  - Woogeun Rhee
  - et al.
- 2007
- ISSCC 2007
A 10Gb/s 5-tap-DFE/4-tap-FFE transceiver in 90nm CMOS
- - M. Meghelli
  - S. Rylov
  - et al.
- 2006
- ISSCC 2006
A 0.18μm SiGe BiCMOS receiver and transmitter chipset for SONET OC-768 transmission systems
- - Mounir Meghelli
  - Alexander V. Rylyakov
  - et al.
- 2003
- ISSCC 2003
Low-power CMOS integrated circuit for field-powered radio frequency identification tags
- - D. Friedman
  - H. Heinrich
  - et al.
- 1997
- ISSCC 1997
A 72-GS/s, 8-Bit DAC-Based Wireline Transmitter in 4-nm FinFET CMOS for 200+ Gb/s Serial Links
- - Timothy O. Dickson
  - Zeynep Toprak Deniz
  - et al.
- 2023
- IEEE JSSC
A 28 GHz hybrid PLL in 32 nm SOI CMOS
- - Mark Ferriss
  - Alexander Rylyakov
  - et al.
- 2014
- IEEE JSSC
A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing
- - Bodhisatwa Sadhu
  - Mark A. Ferriss
  - et al.
- 2013
- IEEE JSSC